The present invention relates to a method for manufacturing an active matrix liquid crystal display ("AMLCD") comprising thin film transistors ("TFT"), and to a structure of the AMLCD manufactured by such a method.
In general as depicted in FIGS. 1 and 2, the AMLCD comprises a substrate ("first substrate") 3 on which a plurality of pixel electrodes 4 are arrayed in a matrix form. Each pixel electrode 4 on the first substrate 3 is bounded by two gate bus lines 17 and two source bus lines 15, each gate bus line 17 being perpendicular with each source bus line 15. The gate bus lines 17 are horizontally formed, and a plurality of gate electrodes 7 perpendicularly branch out from the gate bus lines 17. The source bus lines 15 are vertically formed, and a plurality of source electrodes 5 perpendicularly branch out from the source bus lines 15.
The TFTs are formed near the crossing points of the gate bus lines 17 and the source bus lines 15 and are electrically connected with the pixel electrodes 4. An alignment film (not depicted) which sets the original direction of liquid crystal is formed on the TFTs and the pixel electrodes 4.
The AMLCD also comprises another substrate ("second substrate") 2 on which a color filter layer (not depicted), common electrodes (not depicted) and an alignment film (not depicted) are formed. The first and second substrates 3 and 2 are joined facing each other, and liquid crystal is injected into the space between the alignment films of the first and second substrates 3 and 2. The first and second substrates 3 and 2 have polarizing films 1A and 1B on their outer sides. The AMLCD is manufactured by combining the above mentioned constituents.
Among the above mentioned constituents, the method for manufacturing a first substrate is described below with reference to the drawings.
As shown in FIG. 3A, a Cr layer is deposited on a transparent glass substrate 10. A photo-resist is coated on the Cr layer and the photo-resist is developed into a desired pattern by using a pre-fabricated mask. A gate bus line 17 and a gate electrode 7, which branches out from the gate bus line 17, are formed by etching a portion of the Cr layer along the developed pattern of the photo-resist (FIG. 3A). Afterward, a SiNx film (from which a gate insulating layer 9 is formed later), an amorphous silicon ("a-Si") film (from which a semiconductor layer 11 is formed later), and an n.sup.+ a-Si film (from which an ohmic contact layer 12 is formed later).
Subsequently, a photo-resist is coated on the n.sup.+ a-Si film and the photo-resist is developed into a desired pattern by using a mask. An ohmic contact layer 12 and the semiconductor layer 11 are formed by etching the n.sup.+ a-Si film and the a-Si film at the same time along the developed pattern (FIG. 3C).
Then, Cr is deposited by sputtering on the gate insulating layer 9, the ohmic contact layer 12 and the semiconductor layer 11. A photo-resist is coated on the Cr layer and the photo-resist is developed into a desired pattern by using a mask. A source bus line 15 (functioning as a signal line), a source electrode 5 (which branches out from the source bus line 15) and a drain electrode 6 (functioning as an output electrode) are formed by etching the Cr layer along the developed pattern. The middle of the ohmic contact layer 12 is etched by using the source and drain electrodes as etching masks, so that the ohmic contact layer 12 is separated into two parts (FIG. 3D).
Thereafter, a passivation layer 13 is coated on the gate insulating layer 9, the source bus 15, the source terminal 5, the drain terminal 6, the ohmic contact layer 12 and the semiconductor layer 11. A photo-resist is coated on the passivation layer 13 and the photo-resist is developed into a desired pattern by using a mask. A contact hole 16 is formed in a portion of the passivation layer 13 on the drain electrode by etching the passivation layer 13 along the developed pattern (FIG. 3E).
An ITO (Indium Tin Oxide) layer is formed by sputtering onto the passivation layer 13 and the drain terminal 6 (at the contact hole). A photo-resist is coated on the ITO layer and the photo-resist is developed into a desired pattern by using a mask. A pixel electrode 4 is formed by etching the ITO layer along the developed pattern of the photo-resist (FIG. 3F).
As described above, in the conventional method for manufacturing the AMLCDs, the mask process needs to be used five times in order to manufacture the pixel electrode 4.
The mask process comprises the steps of depositing a film on a substrate and rinsing the surface of the film, coating a photo-resist on the rinsed surface of the film, exposing and developing the photo-resist by using a mask, etching the film along the developed pattern of the photo-resist and removing the photo-resist on the patterned film.
As described above, the mask process is not only complicated but also takes much time and results in relatively high rate of defects. Accordingly, if possible, it is preferable to reduce the number of times in which the mask process is used because defects are increased in proportion to the number of times in which the mask process is used.
Furthermore, as shown in FIG. 3F, level-differences (i.e., non-planar portions) exist in the completed TFT. As a result, defects during a subsequent rubbing operation can occur.